If you create your circuit board layout with the EAGLE program from AUTODESK, please observe the following tips. Basically, it makes sense to use all the prescribed standard-layers of EAGLE.
We are happy to take care of generating the production data (Extended Gerber) for you. You just have to send us your *. brd file along with your order. All further steps are taken care of by our CAM engineers.
We naturally import your ODB++, Gerber-, KiCad-, OrCAD-, Target-, Eagle-, Altium-, IPC-2581-, DPF- and Sprint layout data free of charge!
Instead of the uncommon IPC-2581 format we recommend ODB ++ data!
Multi-CB parameters
For an optimal result, please define the free-of-charge high-tech parameters of Multi-CB:
- Track-width / space: 0.1mm (100µm) - free-of-charge ✓
- Annular ring: 0.1mm (100µm) - free-of-charge ✓
- Drills: 0.2mm (200µm) - free-of-charge ✓
- Via-Pad: 0.4mm (400µm) - free-of-charge ✓
This guarantees the best technology at the best price. The minimum possible values can be found here: Circuit board design parameters.
AUTODESK Fusion 360 - Notes
When using AUTODESK Fusion 360, please export the EAGLE .brd file as "EAGLE 9.X brd compatible files". Otherwise, corrupt data may occur.
Alternatively you can export Gerber data directly from Fusion360.
Go to the MANUFACTURING tab and click on the CAM export icon.
Design Rule Check: .dru file
To ensure the correct settings for your DRC, please use the corresponding EAGLE .dru file, which guarantees that we can produce your circuit boards free of errors. We have created a .dru file for each of the most common board setups.
Please download and unzip the file Multi-CB.dru-files directly into your "dru" directory of EAGLE. Thus, you can select the suitable variant within the software.
From version 7.5 of the EAGLE software, our design rule files are already included.
Standard layers
To convert your EAGLE files, we use Eagle standard layers. Please specify any variations or extended layer specifications with your order.
* Except the inner layer is a negative layer (e.g. ground plane)
Function | EAGLE name | EAGLE layer |
---|---|---|
Top Layer | top | 1 |
pads | 17 | |
vias | 18 | |
Inner layer 2 | Route2 | 2 |
* | pads | 17 |
* | vias | 18 |
Inner layer 3 | Route3 | 3 |
* | pads | 17 |
* | vias | 18 |
Inner layer n | Route(n) | n |
* | pads | 17 |
* | vias | 18 |
Bottom Layer | bottom | 16 |
pads | 17 | |
vias | 18 | |
Solder-stop Top | tstop | 29 |
Solder-stop Bottom | bstop | 30 |
Marking Print | tplace (f.e. ) | 21 |
tnames (z.B. R1) | 25 | |
bnames | 26 | |
Contour, milling, scoring, NPTH slits | dimension | 20 |
PTH slits | milling | 46 |
drills pth (plated-through) | drills | 44 |
drills npth (non-plated-through) | holes | 45 |
* Except the inner layer is a negative layer (e.g. ground plane)
The dimension layer 20 is only for display of the (outer and inner) milling contours with a line thickness of 1mil.
The milling contours including the milling diameter are defined in the milling layer 46.
Npth drill holes that are placed in the dimension layer will not be considered!
Rasterize copper areas
For a better quality of the circuit boards, we generally recommend to rasterize the copper areas, except for high frequency circuit boards with sensitive HF interconnects.
Advantages:
- More consistent copper within the throughplating of the vias.
- Lower risk of Twist & Bow (see also Copper Balance)
1) Ratsnest
To make the filling of the copper areas (polygons) visible, run the command "Rats Nest".
2) Properties
Click on the dotted frame of the copper area in (I)nfo mode to mark it, then click the area again to open the "Properties window".
3) Polygon Pour
In the Properties window, please choose:
- Polygon Pour: hatch
- Width: stands for the line-width of the raster (e.g. 8 mil)
- Spacing: stands for the line spacing of the raster, recommended is 3 x line width (e.g. 24 mil)
Cover vias with solder-stop
In the design rules, the [Masks] settings include the solder-stop mask (Stop) and the solder paste mask (Cream). Depending on the drill diameter, the Limit determines whether a via should be covered with solder-stop or not.
By default, the Limit value is set to 0. This means that all vias are free of solder-stop. If Limit is e.g. set to 8mil (200μm), all vias up to a drilling diameter of 200μm are covered with solder-stop, all larger vias remain free of solder-stop.
see also Via Covering
For a Via which is below the Limit value, you can set a STOP-Flag with CHANGE STOP ON. It is then free from solder-stop.
Marking print
Before creating text, you should always activate the option “vector font” in the text properties.
Otherwise your marking print will very probably be incorrectly applied (see EAGLE 5-Manual, page 44).
Marking print on panels
When copying and pasting the PCB layout during panel creation, it will happen that EAGLE "increments" the component names, since only one unique component name is permitted at a time; e.g., the designation R116 on the original board becomes R156 on the copy.
EAGLE provides the panelize.ulp function for this purpose, but this is only a limited remedy, since corresponding layers are not corrected, but copied to new layers. Usually, for example, layers 25 (tnames) and 26 (bnames) are transferred to the new layers 125 and 126, respectively.
Unfortunately, Multi-CB cannot offer a technical context check of your data, so in these cases it is mandatory to explicitly name the layers to be used as substitutes in the order form (e.g. "marking print top from layer 21 and 125!").
Alternatively, you can also perform the Gerber export of the data directly from EAGLE and send us only the Gerber export.
EAGLE Boardfile < version 4
In the EAGLE versions prior to version 4, the values of solder-stop oversize, solder paste and stop limit have been set directly at the output of Gerber data. These are not included in the boardfile (.brd). Only with version 4 (or higher) and the new DRC, these values are stored in the boardfile.
Boardfiles of EAGLE < version 4 use the default values (as in EAGLE V3.5x 10 mil for solder-stop oversize and stop limit 0).
If you send us boardfiles of an EAGLE version < 4, please clarify the abovementioned export parameters with our technicians (e.g. for covered vias). To avoid errors, we recommend upgrading to a newer EAGLE version.
EAGLE-Bug
The program Eagle 4.11 contains an error that can lead to non-functional circuit boards. Here is the original notice from Cadsoft:
Due to a recent problem that has occurred to an EAGLE user we would like to inform you about a bug in EAGLE version 4.11, which could lead to non-functional boards.
The problem occurs if a user creates a board with EAGLE version 4.09 (or earlier), in which he uses polygons (for instance for supply signals) and places rectangles in the layer tRestrict, bRestrict or 1 through 16, respectively, in such a way that there are places where a polygon can only "flow" through with exactly its own line width. If the CAM data is then generated with EAGLE version 4.11 it can happen that polygons are not calculated in the same way as seen by the user with his version of EAGLE. This in turn may cause some parts not to be connected, and render the board non-functional.
The bug was present in all EAGLE versions from 4.10r01 to 4.11. It is fixed in the current version 4.11r2 (and all beta versions since 4.11r01). Therefore we strongly advise to use the latest version of EAGLE, which is available for download from our homepage.
Checking of Gerberdata
In addition to our free import service for your data, you can also export your own Gerber data. Please use Gerber RS-274X.
Your exported Gerber files can be checked and printed with the freeware Gerbv or GC PREVUE. This allows testing if everything was exported correctly.
Gerbv and GC PREVUE can be found on our download page.
EAGLE Tutorial
The following EAGLE tutorial should just offer a good start to the program for beginners or trainees.